For a high performance CMOS device, the inversion capacitance-based oxide-equivalent thickness of the gate dielectrics (Tinv) needs to be scaled down below 16 Å for future technologies. Traditional oxynitride as a gate dielectric material is reaching its technological limits.
In future technology generations, it is highly desirable to replace a silicon dioxide or silicon oxynitride dielectric with a gate material that has a higher dielectric constant. These materials are known as “high k” materials with the term “high k” denoting an insulating material whose dielectric constant is greater than 4.0, preferably greater than about 7.0. The dielectric constants mentioned herein are relative to a vacuum unless otherwise specified. Of the various possibilities, transitional metal oxides, silicates, or oxynitrides such as hafnium oxide, hafnium silicate, or hafnium silicon oxynitride may be the most suitable replacement candidates for conventional gate dielectrics due to their high dielectric constant and relatively low electrical leakage. In addition, Hf-based compounds exhibit a superior thermal stability at high temperatures with respect to other transitional-metal-based insulating compounds and, therefore, are highly preferred. However, high-k gate dielectric materials and related gate structures should simultaneously possess a number of properties to be useful for state-of-the-art MOSFET devices. Suitable combination of these properties is difficult to achieve with known high-k materials, conventional gate structures, and conventional methods of manufacture.
First, as alluded to above, the suitable high-k containing gate dielectric should be “electrically thin” when the gate is biased in inversion creating a large surface density of mobile inversion charge in the transistor channel. The term “electrically thin” denotes a high capacitance per unit area. It is customary to express the inversion capacitance per unit area in terms of equivalent oxide thickness, Tinv. For the purpose of this invention, Tinv is equal to the absolute dielectric constant of silicon dioxide (˜0.345 pF/cm) divided by the measured value of capacitance per unit area in inversion. For instance, a capacitance per unit area in inversion of about 2.16e−6 F/cm2 corresponds to the Tinv of about 16 A. In turn, the gate dielectric capacitance in inversion consists of several parts including the capacitance of dielectric material itself, the so-called quantum mechanical capacitance associated with a finite size of mobile carrier wave function, and the so-called depletion capacitance of adjacent gate electrode. The inversion capacitance breakdown of Tinv for a state-of-the-art MOSFET is as follows: about 3-5 A for the quantum mechanical portion, about 2-5 A for the gate electrode depletion portion, and about 12-14 A for the gate dielectric material itself. One skilled in the art would appreciate the fact that in order to achieve Tinv of about 16 A with a high-k containing insulating material with a thickness-average k of about 7, the total physical thickness of such high-k containing insulating film should be less than 20 A.
Second, in “high k” material compounds, a metal-oxygen bond is easily polarizable under an external electric filed yielding a high dielectric constant (high-k). The very same high polarizability of these bonds results in a scattering of channel mobile charges by remote phonons present in the high-k material. As a result, the transistor drive current can be substantially reduced by the presence of high-k materials in the gate insulator. It is also known that the proximity of the high-k film to the transistor channel plays a major role in the amount of such highly undesirable remote phonon scattering. The closer the high-k material is to the channel, the stronger the remote phonon scattering. Accordingly, it is extremely difficult to achieve an ultra-thin high-k-containing gate insulator that does not degrade the carrier mobility in the transistor channel.
Third, the entire gate structure including the MOSFET channel region, gate dielectric, and gate electrode should be able to support a state-of-the-art CMOS technology with a low transistor threshold voltage from about 0.1V to about 0.4V. While a desirable threshold voltage can be achieved by varying channel doping and selecting a correct work-function of the gate electrode, it can be inadvertently altered by the presence of a large fixed and/or trapped charge at both gate dielectric interfaces and within the dielectric itself. Further, the density of trapped and/or fixed charge can be inadvertently altered by various processes such as exposure to high-temperature (e.g. a 1000 C. junction activation anneal) or during FET operation. In addition, a high density of fixed or trapped charges in the vicinity of transistor channel can lead to an excessive coulomb scattering of the channel carriers and can reduce the channel mobility and transistor drive current. Accordingly, it is highly desirable to minimize the total surface density of such fixed and/or trapped charge to prevent any undesirable shifts in threshold voltage and channel mobility. Typically, the total surface density of fixed and/or trapped charge should be below 8e−7 C.·cm−2 or, equivalently, the surface number density of charged sites should be below about 5e12 cm−2 for a single charged site. A charge density of 8e−7 C.·cm−2 shifts the threshold voltage by about 0.4V for a gate dielectric with capacitance per unit area in inversion of about 2e−6 F·cm−2.
For example, FIG. 1(a) illustrates a conventional approach for fabricating a high-k gate stack 10 where Si substrate 12 has a base oxide layer 14 comprising SiO2 (or a silicon oxynitride—SiON), for example, and a Hf-silicate layer (e.g., HfxSi1-xO2) 16 formed on the base oxide. Typically, the HfxSi1-xO2 layer is deposited by a chemical vapor deposition (CVD) process, and more specifically, by either an Atomic Layer Deposition (ALD) CVD process or Metal-Organic CVD (MOCVD) process, or like deposition methods. Due to the nucleation problem of either of the aforementioned CVD methods, the HfSiO2 film becomes discontinuous at region 20, when the film is thinner than about 20 Å, as shown in the TEM photograph provided in FIG. 2. As a result, leakage current increases dramatically as the high-K film is thinned. Further, the highly non-uniform or discontinuous high-k film modulates the electrochemical potential in the transistor channel, and hence, reduces the transistor current. Thus, poor thickness scalability of high-k films results from conventional methods such as the kind illustrated in FIG. 1. Further, a 15-20 Å-thick base oxide film 14 is clearly visible in FIG. 2. The base oxide dielectric constant is not high (between 3.9 and about 6) resulting in an additional 10-15 Å of Tinv. As a result, typical Tinv of the insulating stack 14/16 with a continuous 20 Å-thick HfSiO2 film has the following components: dielectric material 14-20 Å, quantum-mechanical 3-5 Å, and depletion of a conventional polysilicon gate electrode 2-5 Å. That is, it is very difficult to scale down a high-k containing insulating layer to meet the requirement of high performance devices (e.g. Tinv<=16.5 A).
FIG. 3 depicts a graphic diagram plotting Tinv vs. a leakage current metric (Toxgl) for the HfO2 stack. For the purpose of this invention, Toxgl is a physical thickness of pure silicon oxide layer that yields the same leakage current density at the same inversion bias as the measured leakage current density of the sample under test in inversion bias. The conversion of measured leakage current density into the Toxgl metric is typically calibrated for thicker silicon oxide films and then extrapolated for ultra thin films using well-known direct tunneling laws of physics. As shown in FIG. 3, when the physical thickness of the HfO2 is reduced from 20 Å to 15 Å, the leakage current density increases by about 1 to 2 orders of magnitude (as reflected in Toxgl reduced from 2.3 nm to 2.1 nm), while Tinv is nearly unchanged. If the base oxide were thinned down, the channel electron mobility will reduce significantly as shown in FIG. 4, due to the remote phonon scattering and coulomb scattering. For example, a dielectric gate stack 14/16 with a 7-10 Å-thick base oxide film 14 followed by a 25-30 Å-thick HfO2 film 16 results in a reduction of peak channel mobility by more than 50% as shown in FIG. 4. The mobility degradation for thinner high-k containing dielectrics is another fundamental challenge for conventional gate dielectric structures and methods of manufacture.
Furthermore, in another conventional approach for fabricating a high-k gate stack structure 25 as illustrated in FIG. 1(b), a Si substrate 12 includes a layer of HfxSi1-xO2 24 deposited directly thereon without a base oxide (e.g., SiO2 or oxynitride). The structure 25 depicted in FIG. 1(b) further exhibits a high density of interface traps, low mobility and poor thermal stability. If heated above about 500 C., the HfxSi1-xO2 layer 24 reacts with underlying substrate 12 to form a thick layer of base oxide (10 Å-15 Å) yielding final gate dielectric structure similar to that of FIG. 1(a). Accordingly, the structure illustrated in FIG. 1(b) has the same fundamental challenges as that of the structure illustrated in FIG. 1(a).
U.S. Pat. No. 6,624,093 (the '093 Patent) entitled METHOD OF PRODUCING HIGH DIELECTRIC INSULATOR FOR INTEGRATED CIRCUIT proposes a method of forming hafnium silicate by depositing hafnium on a silicon dioxide surface of a silicon wafer and then heating the wafer to produce hafnium silicate. The resulting structure includes a high-k layer only and includes a method step of depositing a metal Hf directly on an SiO2 layer. The benefit of this structure is only in the provision of the high-k dielectric due to high dielectric constant without attendant reduction in Tinv to below 16 Å. Furthermore, the '093 Patent does not teach any solution to the degraded channel mobility in the case of thin high-k containing dielectrics with Tinv<16 Å. Subsequently, methods taught in the '093 Patent are only useful for forming relatively thick high-k containing gate dielectrics that do not suffer much from the mobility degradation effects.
U.S. Pat. No. 6,342,414 (the '414 Patent) and U.S. Pat. No. 6,475,874 (the '874 patent) both entitled DAMASCENE NiSi METAL GATE HIGH-K TRANSISTOR propose a method of forming metal silicide gate by confining a low temperature silicidation metal within a recess which is overlaying on the channel. In the recess area, the high-k dielectric is deposited first. Then, a fully-silicided (FUSI) gate layer is formed by depositing a silicon layer on metal layer and then annealing (in the '414 Patent) or, a FUSI layer is formed by depositing a metal layer on silicon layer and then annealing (in the '874 Patent). In these references, the high-k layer and FUSI are formed in two separate steps. High-k is deposited in advance. Then, Si and metal (or vice versa) are deposited and annealed to form the FUSI. The structure and method disclosed in this patent does not solve the aforementioned high-k scaling problems even though, generally, silicide-based, metal-based, and metallic compound-based (e.g. conductive metal nitrides, borides, carbides, oxides, etc.) gate electrodes result in the reduction or elimination of the depletion portion of Tinv. Since high-k dielectric is deposited by a regular method (either PVD or CVD), the physical thickness of the high-k film made by these methods is limited to about 20 Å in addition to 15-20 Å of the SiON base layer needed for acceptable channel mobility as discussed above. As a result, the Tinv of such conventional high-k containing dielectric and FUSI gate electrode is above about 20 Å. Alternatively, the channel mobility is substantially degraded for base SiON layers thinner than about 15 Å and overall Tinv thinner than about 18 Å. While there are numerous instances of prior art teachings where conventional high-k containing films are employed as gate dielectrics in combination with metal gate structures, the resultant transistor gate structures suffer from the same drawbacks as in the '414 Patent and the '874 Patent. Accordingly, it would be highly desirable to enable physical scaling of the high-k containing gate dielectric layer into the 10 Å-20 Å regime without any substantial mobility degradation.
Related co-pending U.S. patent application Ser. No. 10/869,658 (the '658 Patent Application), assigned to the assignee hereof and incorporated herein by reference in its entirety, entitled “High-temperature stable gate structure with metallic electrode” teaches the use of an ultra thin layer of reactive transitional metal such as titanium on top of the slightly thickened base oxide in the range of from about 13 Å to about 20 Å. During a high temperature step, the reactive metal reacts with the base oxide in a non-oxidizing ambient yielding an ultra thin layer of high-k material. In order to make the resultant high-k film thin and insulating, the application teaches that the metal layer should be as thin as possible but still uniform. This can be accomplished if the metal film is thicker than one monolayer and is deposited by a technique that does not have any nucleation problems in such thin regime. Unfortunately, PVD (physical vapor deposition or sputtering) deposition technique employed in the '658 Patent Application results in damage to the base oxide film by energetic ions. In addition, the method is limited to highly reactive titanium atoms which are known to react with silicon oxide at a relatively low temperature of below about 700 C.
Therefore, a new solution is needed to solve the aforementioned problems with the prior art conventional approaches.